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ns7520 data sheet t he digi ns7520 is a high-perform ance, highly integrated, 32-bit system-on-a chip asic designed for use in intelligent networked devices and in ternet appliances. the ns7520 is based on the standard architecture in the net+arm ? family of devices. the ns7520 can support most any networking scenario, and includes a 10/100 baset ethernet mac and two independent serial ports (each of which can run in uart or spi mode). the cpu is an arm7tdmi 32-bit risc processor core with a rich complement of supp ort peripherals and memory controllers for various types of memory (including flash, sdram, eeprom, and others), programmable timers, a 13-channel dma controller, an external bus expansion module, and 16 general-purp ose input/output (gpio) pins. net+arm is the hardware foundation for the net+works ? family of integrated hard ware and software solutions for device networking. these comprehensive platforms include drivers, popu lar operating systems, networking software, development tools, apis, and complete development boards.

contents iii ns7520 overview........................................................................... 1 key features................................................................................ 2 operating frequency ...................................................................... 3 packaging and pinout ..................................................................... 4 pinout detail tables ....................................................................... 6 system bus interface............................................................. 6 chip select controller........................................................... 10 ethernet interface mac......................................................... 11 ?no connect? pins ............................................................... 13 general purpose i/o ............................................................ 13 system clock and reset ......................................................... 15 system mode (test support) ................................................... 16 jtag test ......................................................................... 16 power supply ..................................................................... 17 ns7520 modules........................................................................... 18 cpu module ...................................................................... 18 gen module ...................................................................... 18 system (sys) module............................................................ 18 bbus module...................................................................... 19 memory module (mem).......................................................... 19 dma controller ................................................................... 19 ethernet controller.............................................................. 19 serial controller ................................................................. 21 ns7520 bootstrap initialization ......................................................... 22 jtag ............................................................................... 22 arm debug........................................................................ 22 dc characteristics and other operat ing specifications.............................. 23 absolute maximum ratings..................................................... 24 pad pullup and pulldown char acteristics .................................... 24 ac characteristics .................. ...................................................... 25 ac electrical specifications .................................................... 25 oscillator characteristics..... ........................................................... 27 timing diagrams .......................................................................... 28 timing_specifications........................................................... 28 reset_timing ..................................................................... 29 sram timing ...................................................................... 30 sdram timing .................................................................... 40 fp dram timing .................................................................. 48 ethernet timing .................................................................. 55 jtag timing ...................................................................... 57 external dma timing ............................................................ 59 serial internal/external ti ming................................................ 61 gpio timing....................................................................... 63

ns7520 overview www.digi.com 1 ns7520 overview figure 1 shows the ns7520 modules. da shed lines indicate shared pins. figure 1: ns7520 module overview debugger pll system clock jtag debug interface arm7tdmi firq irq 2 timers watchdog timer power 3.3v 1.5v bbus d m a d m a d m a d m a serial-a uart spi serial-b uart spi 4 level interrupt inputs 16 gpio ethernet controller 802.3 compliant external memory controller ns7520 reset address bus serial transceivers and other devices mii memory devices flash sram fp dram sdram boot config
key features 2 ns7520 datasheet 03/2006 key features this table lists the key features of the ns7520. cpu core integrated 10/100 ethernet mac arm7tdmi 32-bit risc processor 32-bit internal bus 32-bit arm and 16-bit thumb mode 15 general purpose 32-bit registers 32-bit program counter (pc) and status register five supervisor modes, one user mode 10/100 mbps mii-based phy interface 10 mbps endec interface tp-pmd and fiber-pmd device support full-duplex and half-duplex modes optional 4b/5b coding station, broadcast, and multicast address detection 512-byte transmit fifo , 2 kbyte receive fifo intelligent receive-side buffer selection 13-channel dma controller programmable timers two channels dedicated to ethernet transmit and receive four channels dedicated to two serial modules? transmit and receive four channels for external peripherals. only two channels ? either 3 and 5 or 4 and 6 ? can be configured at one time. three channels availabl e for memory-to-memory transfers flexible buffer management two independent timers (2 s?20.7 hours) watchdog timer (interrupt or reset on expiration) programmable bus monitor or timer general purpose i/o pins operating frequency 16 programmable gpio interface pins 4 pins programmable with level-sensitive interrupt 36, 46, or 55 mhz internal clock operation from 18.432 mhz crystal f max = 36, 46, or 55 (grade?dependent) system clock source by external quartz crystal or crystal oscillator, or clock signal programmable pll, which allows a range of operating frequencies from 10 to f max maximum operating frequency from external clock or using pll multiplication f max
operating frequency www.digi.com 3 operating frequency the ns7520 is available in grades operating at three maximum operating frequencies: 36 mhz, 46 mhz, and 55 mhz. the operating frequency is set during bootstrap initialization, using pins a[8:0]. these address pins load the pll settings re gister on powerup reset. a[8:7] determines is (charge pump current); a[6:5] determines fs (output divider), and a[4:0] defines nd (pll multiplier). each bit in a[8:0] can be set individual ly. see the discussion of the pll settings register in the ns7520 hardware reference for more information. serial ports bus interface two fully independent serial ports (uart, spi) digital phase lock loop (dpll) for receive clock extractions 32-byte transmit/receive fifos internal programmable bit-rate generators bit rates 75?230400 in 16x mode bit rates 1200 bps?4 mbps in 1x mode flexible baud rate generator, external clock for synchronous operation receive-side character and buffer gap timers four receive-side data match detectors five independent programmable chip selects with 256 mb addressing per chip select chip select support for sram, fp/edo dram, sdram, flash, and eeprom without external glue 8-, 16-, and 32-bit peripheral support external address decodi ng and cycle termination dynamic bus sizing internal dram/sdram controller with address multiplexer and programmable refresh frequency internal refresh controller (cas before ras) burst-mode support 0?63 wait states per chip select address pins that configurem chip operating modes (see "ns7520 bootstrap initialization" on page 22) power and operating voltages 500 mw maximum at 55 mhz (all outputs switching) 418 mw maximum at 46 mhz (all outputs switching) 291 mw maximum at 36 mhz (all outputs switching) 3.3 v ? i/o 1.5 v ? core
packaging and pinout 4 ns7520 datasheet 03/2006 packaging and pinout table 1 provides the ns7520 packaging dimens ions. figure 2 shows the ns7520 pinout and dimensions. symbol min nom max a ??1.4 a1 0.35 0.40 0.45 a2 ??0.95 b 0.45 0.50 0.55 d 13.0 bsc d1 11.2 bsc e 13.0 bsc e1 11.2 bsc e 0.8 bsc aaa 0.1 table 1: ns7520 packaging dimensions
packaging and pinout www.digi.com 5 figure 2: ns7520 pinout and dimensions 177 pfbga
pinout detail tables 6 ns7520 datasheet 03/2006 pinout detail tables each pinout table applies to a specific inte rface and contains the following information: notes: no connect as a pin description means do not connect to this pin . the 177th pin (package ball) is for alignment of the package on the pcb. system bus interface signal the pin name for each i/o signal. some signals have multiple function modes and are identified accordingly. the mode is configured through firmwa re using one or more configuration registers. pin the pin number assignment for a specific i/o signal. u next to the pin number indicates that the pin is a pullup resistor. d next to the pin number indicates th at the pin is a pulldown resistor. no value next to the pin indicates that the pin has neither a pullup nor pulldown resistor. see figure 5, "internal pullup characteristic s," on page 24 and figure 6, "internal pulldown characteristics," on page 25 for an illustration of th e characteristics of these pins. use the figures to select the appropriate value of the complime ntary resistor to drive the signal to the opposite logic state. for those pins with no pullup or pu lldown resistor, you must select the appropriate value per your design requirements. _ an underscore (bar) indicates that the pin is active low . i/o the type of signal ? input, output, or input/output. od the output drive strength of an output buffe r. the ns7520 uses one of three drivers: 2 ma 4 ma 8 ma symbol pin i/o od description bclk a6 0 8 synchronous bus clock external bus other external bus other addr27 cs0oe_ n10 u i/o 4 addr bit 27 logical and of cs0_ and oe_ addr26 cs0we_ p10 u i/o 4 addr bit 26 logical and of cs_ and we_ external bus external bus addr25 m10 u i/o 4 remainder of address bus (through addr0) addr24 r10 u i/o 4 addr23 n9 u i/o 4 addr22 r9 u i/o 4 addr21 m9 u i/o 4
system bus interface www.digi.com 7 addr20 n8 u i/o 4 addr19 p8 u i/o 4 addr18 m7 u i/o 4 addr17 r7 u i/o 4 addr16 n7 u i/o 4 addr15 r6 u i/o 4 addr14 m6 u i/o 4 addr13 p6 u i/o 4 addr12 n6 u i/o 4 addr11 m5 u i/o 4 addr10 p5 u i/o 4 addr9 n5 u i/o 4 addr8 r4 u i/o 4 addr7 r3 u i/o 4 addr6 r2 u i/o 4 addr5 m4 u i/o 4 addr4 n4 u i/o 4 addr3 r1 u i/o 4 addr2 m3 u i/o 4 addr1 n2 u i/o 4 addr0 p1 u i/o 4 data31 n1 i/o 4 data bus data30 m1 i/o 4 data29 l3 i/o 4 data28 l2 i/o 4 data27 l4 i/o 4 data26 l1 i/o 4 data25 k3 i/o 4 data24 k2 i/o 4 data23 k1 i/o 4 data22 j2 i/o 4 data21 j3 i/o 4 data20 j1 i/o 4 symbol pin i/o od description
system bus interface 8 ns7520 datasheet 03/2006 data19 h3 i/o 4 data18 h4 i/o 4 data17 h1 i/o 4 data16 h2 i/o 4 data15 g4 i/o 4 data14 g1 i/o 4 data13 g3 i/o 4 data12 g2 i/o 4 data11 f4 i/o 4 data10 f2 i/o 4 data9 f3 i/o 4 data8 e1 i/o 4 data7 e2 i/o 4 data6 e3 i/o 4 data5 d1 i/o 4 data4 c1 i/o 4 data3 b1 i/o 4 data2 d4 i/o 4 data1 d3 i/o 4 data0 c2 i/o 4 be3_ d9 i/o 2 byte enable d31:d24 be2_ a9 i/o 2 byte enable d23:d16 be1_ c9 i/o 2 byte enable d15:d08 be0_ b9 i/o 2 byte enable d07:d00 ts_ a8 i/o 4 do not use add an external 820 ohm pullup to 3.3 v. ta_ d8 u i/o 4 data transfer acknowledge add an external 820 ohm pullup to 3.3 v. ta_ is bidirectional. it is used in input mode to terminate a memory cycle externally. it is used in output mode for reference purposes only. tea_ c8 u i/o 4 data transfer error acknowledge add an external 820 ohm pullup to 3.3 v. tea_ is bidirectional. it is used in input mode to terminate a memory cycle externally. it is used in output mode for reference purposes only. symbol pin i/o od description
system bus interface www.digi.com 9 system bus interface signal descriptions rw_ d6 i/o 2 transfer direction br_ d7 no connect bg_ c7 no connect busy_ b7 no connect mnemonic signal description bclk bus clock provides the bus clock. all system bus interface signals are referenced to the bclk signal. addr[27:0] address bus identifies the address of the pe ripheral being addressed by the current bus master. the address bus is bi-directional. data[31:0] data bus provides the data transf er path between the ns7520 and external peripheral devices. the data bus is bi-directional. recommendation: less than x32 (s)dram/sram memory configurations. unconnect ed data bus pins will float during memory read cycles. floating inputs can be a source of wasted power. for other than x32 dram/sram configurations, the unused data bus signals should be pulled up. ts_ transfer start no connect be_ byte enable identifies which 8-bit bytes of the 32-bit data bus are active during any given system bus memory cycle. the be_ signals are active low and bi-directional. ta_ transfer acknowledge indicates the end of the current system bus memory cycle. this signal is driven to 1 prior to tri-stating its driver. ta_ is bi-directional. tea_ transfer error acknowledge indicates an error terminati on or burst cycle termination: in conjunction with ta_ to signal the end of a burst cycle. independently of ta_ to signal th at an error occurred during the current bus cycle. tea_ terminates the current burst cycle. this signal is driven to 1 prior to tri-stating its driver. tea_ is bi-directional. the ns7520 or the external peripheral can drive this signal. rw_ read/write indicator indicates the direction of the sy stem bus memory cycle. rw_ high indicates a read operation; rw_ lo w indicates a write operation. the rw_ signal is bi-directional. br_ bus request no connect bg_ bus grant no connect busy_ bus busy no connect symbol pin i/o od description
chip select controller 10 ns7520 datasheet 03/2006 chip select controller the ns7520 supports five unique chip select configurations. chip select controller signal descriptions symbol pin i/o od description cs4_ b4 o 4 chip select/dram ras_ cs3_ a4 o 4 chip select/dram ras_ cs2_ c5 o 4 chip select/dram ras_ cs1_ b5 o 4 chip select/dram ras_ cs0_ d5 o 4 chip select (boot select) cas3_ a1 o 4 fp/edo dram column strobe d31:d24/sdram ras_ cas2_ c4 o 4 fp/edo dram column strobe d23:d16/sdram cas_ cas1_ b3 o 4 fp/edo dram column strobe d15:d08/sdram we_ cas0_ a2 o 4 fp/edo dram column strobe d07:d00/sdram a10(ap) we_ c6 o 4 write enable for ncc ctrl?d cycles oe_ b6 o 4 output enable for ncc ctrl?d cycles mnemonic signal description cs0_ cs1_ cs2_ cs3_ cs4_ chip select 0 chip select 1 chip select 2 chip select 3 chip select 4 unique chip select outputs supported by the ns7520. each chip select can be configured to decode a por tion of the available address space and can address a maximum of 256 mbytes of address space. the chip selects are configured using registers in the memory module. a chip select signal is driven low to indicate the end of the current memory cycle. for fp/edo dram, these signals provide the ras signal. cas0_ cas1_ cas2_ cas3_ column address strobe signals activated when an address is d ecoded by a chip select module configured for dram mode. the cas_ signals are active low and provide the column address strobe function for dram devices. the cas_ signals also identify which 8-bit bytes of the 32-bit data bus are active during any given system bus memory cycle. for sdram, cas[3:1]_ provides the sdram command field. cas0_ provides the auto-precharge signal. for non-dram settings, these signals are 1. we_ write enable active low signal that indicates that a memory write cycle is in progress. this signal is activate d only during write cycles to peripherals controlled by one of the chip selects in the memory module. oe_ output enable active low signal that indicates that a memory read cycle is in progress. this signal is activate d only during read cycles from peripherals controlled by one of the chip selects in the memory module.
ethernet interface mac www.digi.com 11 ethernet interface mac note: endec values for general-purpos e output and txd refer to bi ts in the ethernet general control register. endec values for general-pu rpose input and rxd refer to bits in the ethernet general status register. in this table, gp designates general-purpose . ethernet interface mac signal descriptions the ethernet mii (media independen t interface) provides the connec tion between the ethernet phy and the mac (media access controller). symbol pin i/o od description mii endec mii endec mdc gp output d10 o 2 mii management clock state of (lpbk bit xor (mode=seeq)) mdio gp output b10 u i/o 2 mii data state of utp_stp bit txclk c10 i tx clock txd3 gp output a12 o 2 tx data 3 state of aui_tp[0] bit txd2 gp output b11 o 2 tx data 2 state of aui_tp[1] bit txd1 gp output d11 o 2 tx data 1 inverted state of pdn bit, open collector txd0 txd a11 o 2 tx data 0 transmit data txer gp output a13 o 2 tx code error state of lnk_dis_ bit txen b12 o 2 tx enable txcol a14 i collision rxcrs d12 i carrier sense rxclk c12 i rx clock rxd3 gp input d14 i rx data 3 read state in bit 12 rxd2 gp input b15 i rx data 2 read state in bit 15 rxd1 gp input a15 i rx data 1 read state in bit 13 rxd0 rxd b13 i rx data 0 receive data rxer gp input c15 i rx error read state in bit 11 rxdv gp input d15 i rx data valid read state in bit 10
ethernet interface mac 12 ns7520 datasheet 03/2006 mnemonic signal description mdc mii management clock provides the clock for the mdio serial data channel. the mdc signal is an ns7520 output. the frequency is derived from the system operating frequency per the clks fiel d setting (see the clks field in table 69: "mii manageme nt configuration register bit definition" on page 191). mdio management data io a bi-directional signal that provides a serial data channel between the ns7520 and the external ethernet phy module. txclk transmit clock an input to the ns752 0 from the external phy module. txclk provides the synchronous data clock for transmit data. txd3 txd2 txd1 txd0 transmit data signals nibble bus used by the ns7520 to driv e data to the external ethernet phy. all transmit data signals are synchronized to txclk. in endec mode, only txd0 is used for transmit data. txer transmit coding error output asserted by the ns7520 when an error has occurred in the transmit data stream. txen transmit enable asserted when the ns7520 drives valid data on the txd outputs. this signal is synchronized to txclk. col transmit collision input signal asserted by th e external ethernet phy when a collision is detected. crs receive carrier sense asserted by the external ethernet phy whenever the receive medium is non-idle. rxclk receive clock an input to the ns7520 fr om the external phy module. the receive clock provides the synchronous data clock for receive data. rxd3 rxd2 rxd1 rxd0 receive data signals nibble bus used by the ns7520 to input receive data from the external ethernet phy. all receiv e data signals are synchronized to rxclk. in endec mode, only rxd0 is used for receive data. rxer receive error input asserted by the exte rnal ethernet phy when the ethernet phy encounters invalid symbols from the network. rxdv receive data valid input asserted by the external et hernet phy when the phy drives valid data on the rxd inputs.
?no connect? pins www.digi.com 13 ?no connect? pins general purpose i/o pin description r13 tie to v cc p12 tie to v cc n12 xtalb1: tie to v cc r15 xtalb2: no connect m11 no connect p11 no connect n11 no connect r12 no connect r14 no connect p13 no connect gpio signal serial signal other signal pin i/o od serial channel description other description porta7 txda j14 u i/o 2 channel 1 txd porta6 dtra_ dreq1_ j13 u i/o 2 channel 1 dtr_ dma channel 3/5 req porta5 rtsa_ j15 u i/o 2 channel 1 rts_ porta4 rxca/ria_/ out1a_ j12 u i/o 2 pgm?able out/ channel 1 rxclk/ channel 1 ring signal/ channel 1 spi clock (clk) porta3 rxda dack1_ h15 u i/o 2 channel 1 rxd dma channel 3/5 ack porta2 dsra_ amux h12 u i/o 2 channel 1 dsr_ dram addr mux porta1 ctsa_ done1_ (o) h13 u i/o 2 channel 1 cts_ dma channel 3/5 done_out porta0 txca/ out2a_/ dcda_ done1_ (i) g12 u i/o 2 pgm?able out/ channel 1 dcd/ channel 1 spi enable (sel_)/ channel 1 txclk dma channel 3/5 done_in portc7 txdb g13 u i/o 2 channel 2 txd gen interrupt out portc6 dtrb_ dreq2_ g14 u i/o 2 channel 2 dtr_ dma channel 4/6 req
general purpose i/o 14 ns7520 datasheet 03/2006 notes: 1 reset output indicates the reset state of the ns 7520. portc4 persists beyond the negation of reset_ for approximately 512 clock cycles if th e pll is disabled. when the pll is enabled, portc4 persists beyond the negation of reset_ to allow for pll lock for 100 microseconds times the ratio of the vco to xtala. this gpio is left in output mode active following a hardware reset. 2 portc[3:0] pins provide level-sensitive interrupt s. the inputs do not need to be synchronous to any clock. the interrupt rema ins active until cleared by a ch ange in the input signal level. portc5 rtsb_ reject_ f15 u i/o 2 channel 2 rts_ cam reject portc4 1 rxcb/rib_/ out1b_ reset_ f12 u i/o 2 pgm?able out/ channel 2 rxclk/channel 2 ring signal/ channel 2 spi clock (clk) reset output portc3 2 rxdb lirq3/ dack2_ f13 u i/o 2 channel 2 rxd level sensitive irq / dma channel 4/6 ack portc2 2 dsrb_ lirq2/rpsf_ e15 u i/o 2 channel 2 dsr_ level sensitive irq/ cam request portc1 2 ctsb_ lirq1/ done2_(o) e12 u i/o 2 channel 2 cts_ level sensitive irq / dma channel 4/6 done_out portc0 2 txcb/ out2b_/ dcdb_ lirq0/ done2_(i) e14 u i/o 2 pgm?able out/ channel 2 dcd/ channel 2 spi enable (sel_)/ channel 2 txclk level sensitive irq / dma channel 4/6 done_in gpio signal serial signal other signal pin i/o od serial channel description other description
system clock and reset www.digi.com 15 system clock and reset signal descriptions the ns7520 has three clock domains: system clock (sysclk) bit rate generation and programmab le timer reference clock (xtala1/2) system bus clock (bclk) the sys module provides the ns7520 with thes e clocks, as well as system reset and backup resources. this figure shows the timing and spec ification for reset_ rise/fall times: symbol pin i/o od description xtala1 k14 i arm/system oscillator circuit xtala2 k12 o pllvdd (1.5v) l15 p pll clean power pllvss l12 p pll return reset_ a10 i system reset mnemonic signal description xtala1 xtala2 oscillator input oscillator output a standard parallel quartz crysta l or crystal oscillator can be attached to these pins to provide the main input clock to the ns7520. pllvdd pllvss clean pll power connect directly to the gnd plane power and ground for pll circuit. reset_ system reset resets the ns7520 hardware. table 2: clock generation and reset signal description tr max = 18ns vi n = 0.8v to 2.0v tf max = 18ns vi n = 2.0v to 0.8v tf tr
system mode (test support) 16 ns7520 datasheet 03/2006 system mode (test support) plltst_, bisten_, and scanen_ primary inputs control different test modes for both functional and manufacturing test operations (see ta ble 3: "ns7520 test modes" on page 22). jtag test jtag boundary scan allows a tester to check th e soldering of all signal pins and tri-state all outputs. arm debugger signal descriptions symbol pin i/o od description plltst_ n15 i encoded with bisten_ and scanen_ add an external pullup to 3.3v or pulldown to gnd. bisten_ m15 i encoded with plltst_ and scanen_ add an external pullup to 3.3v or pulldown to gnd. scanen_ l13 i encoded with bisten_ and plltst_ add an external pullup to 3.3v or pulldown to gnd. symbol pin i/o od description tdi n14 u i test data in. tdo m13 o 2 test data out. tms m12 u i test mode select. trst_ m14 i test mode reset. requires external termination when not being used (see figure 3, "trst_ termination," on page 17 for an illustration of the termination circuit on the development pcb). tck p15 i test mode clock. add an external pullup to 3.3v. mnemonic signal description tdi test data in tdi operates the jtag st andard. consult the jtag specifications for use in boundary-scan testing. these signals meet the requirements of the rave n and jeeni debuggers. tdo test data out tdo operates the jtag standard. consult the jtag specifications for use in boundary-scan testing. these signals meet the requirements of the rave n and jeeni debuggers. tms test mode select tms operates the jtag st andard. consult the jtag specifications for use in boundary-scan testing. these signals meet the requirements of the rave n and jeeni debuggers.
power supply www.digi.com 17 figure 3: trst_ termination power supply trst_ test mode reset trst_ operates the jtag standard. consult the jtag specifications for use in boundary-s can testing. these signals meet the requirements of the raven and jeeni debuggers. tck test mode clock tck operates the jtag st andard. consult the jtag specifications for use in boundary-scan testing. these signals meet the requirements of the rave n and jeeni debuggers. signal pin description oscillator vcc (3.3v) n13, c3 oscillator power supply core vcc (1.5v) r8, l14, c14, c13 core power supply i/o vcc (3.3v) e4, k4, m2, n3, p3, r5, h14, f14, b8, a3 i/o power supply gnd d2, f1, j4, p4, p7, m8, p9, r11, k15, g15, e13, d13, b14, c11, a7, a5, b2, p2, p14, k13 ground mnemonic signal description
ns7520 modules 18 ns7520 datasheet 03/2006 ns7520 modules cpu module the cpu uses an arm7tdmi core processor. the ar m architecture is based on reduced instruction set computer (risc) principles, which result in high instruction throughp ut and impressive real- time interrupt respon se for a small, cost-effective circuit. for more information about arm7tdmi, see the arm7tdmi data sheet from arm ltd. (www.arm.com). gen module the gen module provides the ns7520 with its main system control function s, as well as these features: two programmable timers with interrupt one programmable bus-error timer one programmable watchdog timer two 8-bit programmable general-purpose i/o ports system (sys) module the system module prov ides the system clock (sys_clk) and system reset (sys_reset) resources. the system control signals determin e the basic operation of the chip: signal mnemonic signal name description {xtala1, xtala2} clock source operate in one of two ways: the signals are affixed with a 10-20 mhz parallel mode quartz crystal or crystal oscillator and the appropriate components per the component manufacturer. xtala1 is driven with a clock signal and xtala2 is left open. {pllvdd, pllvss} pll power provide an isolated power supply for the pll. reset_ chip reset active low signal asserted to initiate a hardware reset of the chip. {tdi, tdo, tns, trst_, tck} jtag interface provide a jtag interface for the chip. this interface is used for both boundary scan and ice control of the internal processor. {plltest_, bisten_, scanen_} chip mode encoded to determine the chip mode.
bbus module www.digi.com 19 the ns7520 clock module creates the bclk and fxta l signals. both signals are used internally, but bclk can also be accessed at ball a6 by setting the bclkd field in the system control register to 0. bclk functions as the system clock and provides the majority of the ns7520?s timing. fxtal provides the timing for the dram refres h counter, can be selected instead of bclk to provide timing for the watchdog timer, th e two internal timers, and the serial module. bbus module the bbus module provides the data path among ns7520 internal modules. this module provides the address and data multiplexing lo gic that supports the data fl ow through the ns7520. the bbus module is the central arbiter fo r all the ns7520 bus masters and, once mastership is granted, handles the decoding of each address to one (or none) of the ns7520 modules. memory module (mem) the mem module provides a glueless interface to external memory devices such as flash, dram, and eeprom. the memory controller contains an integrated dram controller and supports five unique chip select configurations. the mem module monitors the bbus interface for ac cess to the bus module; that is, any access not addressing internal resour ces. if the address to be used corres ponds to a base address register in the mem module, the mem module provides the memory access signals and responds to the bbus with the necessary completion signal. the mem module can be configured to interface with fp, edo, or sdram (synchronous dram), although the ns7520 cannot interface with more than one device type at a time. dma controller the ns7520 contains one dma controller, with 13 dm a channels. each dma channel moves blocks of data between memory an d a memory peripheral. the dma controller supports both fly-by op erations and memory-to-memory operations: when configured for fly-by operation, the dma controller transfers data between one of the ns7520 peripherals and a memory location. when configured for memory-to-memory operat ions, the dma controller uses a temporary holding register between read and write operations. two memory cycles are executed. ethernet controller the ethernet controller provides the ns7520 with one ieee 802.3u compatible ethernet interface. the ethernet interface includes the ethernet front-end (efe) an d media access controller (mac). the ethernet module supports both media independent interface (mii) and endec modes.
ethernet controller 20 ns7520 datasheet 03/2006 the mac module interfaces to an external physical layer (phy) device using the mii standard defined by ieee 802.3u. the mac interface includes the mii cloc k and data signals. figure 4 shows a high-level block diagram of th e efe module, which provides the fifo handling interface between the ns7520 bbus and the mac modules. figure 4: efe module block diagram 512 byte local transmit fifo rx filtering & statistics 2k byte local receive fifo mac tx interface mac rx interface bbus
serial controller www.digi.com 21 serial controller the ns7520 supports two independent universal as ynchronous/synchronous receiver/transmitter channels. each channel su pports these features: independent programmable bit-rate generator uart and spi (master) modes high-speed data transfer: ? x1 mode: 4mbits/sec ? x16 mode: 230 kbits/sec 32?byte tx fifo 32?byte rx fifo programmable data format: 5?8 data bits; odd, even, or no parity; 1, 2 stop bits programmable channel modes: normal , local loopback, remote loopback control signal support maskable interrupt conditions: ? receive break detection ? receive framing error ? receive parity error ? receive overrun error ? receive fifo ready ? receive fifo half-full ? transmit fifo ready ? tr a n s m i t f i f o h a l f - e m p t y ? cts, dsr, dcd, ri state change detection clock/data encoding: nrz, nrzb, nrzi, fm, manchester multi-drop capable
ns7520 bootstrap initialization 22 ns7520 datasheet 03/2006 ns7520 bootstrap initialization many internal ns7520 features are configured wh en the reset pin is asserted. the address bus configures the appropriate control register bits at powerup. this table shows which bits control which functions: jtag the ns7520 provides full support for 1149.1 jtag boundary scan testing. all ns7520 pins can be controlled using the jtag interf ace port. the jtag interface provides access to the arm7tdmi debug module when the ap propriate combination of plltst_ , bisten_ , and scanen_ is selected (as shown in table 3: "ns7520 test modes"). arm debug the arm7tdmi core uses a jtag tap controller that shares the pins with the tap controller used for 1149.1 jtag boundary scan testing. to enable the arm7tdmi tap controller, {plltst_,bisten_,scanen_} must be set as shown in table 3: "ns7520 test modes". address bit name description addr[27] endian configuration 0 little endian configuration 1 big endian configuration addr[26] cpu bootstrap 0 cpu disabled; gen_buser=1 1 cpu enabled; gen_buser=0 addr[24:23] cs0/mmcr[19:18] setting 00 8-bit sram, 63 wait-states/b00 01 32-bit sram, 63 wait-states/ b 01 10 32-bit sram 11 16-bit sram, 63 wait-states/b11 addr[19:9] gen_id setting gen_id=a[19:09],default= ?h3ff addr[8:7] pll is setting is=a[8:7], default= ?b10 addr[6:5] pll fs setting fs=a[6:5], default= ?b00 addr[4:0] pll nd setting nd=a[4:0], default= ?b01011 table 3: ns7520 test modes
dc characteristics and othe r operating specifications www.digi.com 23 dc characteristics and othe r operating specifications the ns7520 operates using an internal core v dd supply voltage of 1.5v. a 3.3vc supply is required for the i/o cells, which drive/accept 3.3v levels. table 4 provides the dc characteristics for inpu ts; table 5 provides the dc characteristics for outputs. table 6 defines the dc operating (thermal) conditio ns for the ns7520. operat ing the ns7520 outside these conditions results in unpredictable behavior. sym parameter conditions min typ max unit v ih input high voltage 2.0 3.6 v v il input low voltage v ss ? 0.3 0.8 v table 4: dc characteristics ? inputs sym parameter conditions min max unit p power consumption f sysclk = 55 mhz core i/o f sysclk = 46 mhz core i/o f sysclk = 36 mhz core i/o 508 192 316 425 161 264 333 126 207 mw mw mw mw mw mw mw mw mw v ol output low voltage outputs & bi-directional 0 0.4 v v oh output high voltage outputs & bi-directional 2.4 v dd v table 5: dc characteristics ? outputs sym parameter conditions min typ max unit v dd core supply voltage 1.4 1.5 1.6 v v cc i/o supply voltage 3.0 3.3 3.6 v t op ambient temperature -40 85 o c t j junction temperature 110 o c t stg storage temperature -40 125 o c j pkg thermal resistance 50 o c/w i ih input threshold no pullup -10 10 ? table 6: recommended operating temperatures
absolute maximum ratings 24 ns7520 datasheet 03/2006 absolute maximum ratings this table defines the maximum values for the voltages that the ns7520 can withstand without being damaged. pad pullup and pulldown characteristics figure 5 illustrates characteristics for a pad with internal pullup; figure 6 illustrates characteristics for a pad with internal pulldown. see "pinout detail tables," beginning on page 6, for information about which pins use pullup and pulldown resistors. figure 5: internal pullup characteristics i il input current as ?0? no pullup 10 10 a i oz highz leakage current any input -10 10 a c io pin capacitance v o =0 7 pf sym parameter min max v dd core supply voltage -0.3 3.15 v cc i/o supply voltage -0.3 3.9 v in input voltage -0.3 3.9 v out output voltage -0.3 3.9 sym parameter conditions min typ max unit table 6: recommended operating temperatures
ac characteristics www.digi.com 25 figure 6: internal pulldown characteristics ac characteristics ac electrical specifications define the timing re lationship between signals for interfaces and modes within a given interface. ac electrical specifications the ac electrical specifications are based on the system configuration shown in figure 7, with a 5pf allowance for pcb capacitance and a 0.25 ns allowance for pcb delay. the timing of the buffers, sdram, and the like must be added to co mplete timing analysis. in systems where sdram is not used, two devices are expected to replace the sd rams shown in figure 7; that is, they are tied directly to the chip. system loading information is shown in table 7: "system loading details" on page 26.
ac electrical specifications 26 ns7520 datasheet 03/2006 figure 7: system configuration for specified timing exceeding the loading shown in table 7 can result in additional signal delay. the delay can be approximated by derating the output buffer based on the expected load capacitance per the values shown in table 8. signal estimated load (pf) device loads bclk 23 two sdrams, 1 clock buffer/clock input to pld a[27:0], cas[3:0]_ 23 two sdram a n , 1 buffer/pld cs[4:0]_ 13 two sdram cs n , 1 buffer pld data[31:0] 18 one sdram dq, 1 buffer/pld be*_ 19 one sdram dq, 1 buffer/pld ts_, ta_, tea_, br_, bg_, busy_, we_, oe_ 15 1 buffer/pld porta3, porta1, portc3, portc1 (operating external dma) 15 1 buffer/pld other porta[*] and portc[*], tdo 85 tester load mdc, mdio, txen, txer, txd[3:0] 20 one phy table 7: system loading details signal derating (ns/pf) bclk 0.069 a[27:0], ts_, ta_, tea_, br_, bg_, busy_, data[31:0] 0.150 be[3:0] 0.300 table 8: output buffer derating by load capacitance sdram sdram ns7520 other memory devices buffer
oscillator characteristics www.digi.com 27 oscillator characteristics figure 8 illustrates the recommen ded oscillator circuit details. rise/fall time. the max rise/fall time on the system clock input pin is 1.5ns when used with an external oscillator. duty cycle. the duty cycle is system-dependent with an external oscillator. it affects the setup and hold times of signals that change in the falling clock ed ges, such as we_/oe_. recommendation: use a 3.3v, 5010% duty cycle oscill ator with a 100 ohm series resistor at the output. the plls can handle a 25% duty cycle clock (minimum high/low time 4.5ns). figure 8: oscillator circuit details cs[4:0]_, cas[3:0], rw_, we_, oe_ 0.137 mdc, txd[3:0], txer, txen, tdo 0.274 signal derating (ns/pf) table 8: output buffer derating by load capacitance 3r3v scanen_ pll enabled - u1 & r2 in, r1 out c2 10pf a 18.432mhz crystal or 55.296mhz oscillator allows full speed operation. r4 0 ohm nc u1 lvc04 1 2 3 4 5 reset_ k14 3r3v c3 100nf c1 10pf r2 0 ohm pll bypassed - u1 & r2 out, r1 in r1 10k y2 sm_oscillator 4 2 1 3 vcc gnd test out k12 ns7520 r3 1m r11 100 ohm xtal1 a10 rise time = 18ns; 0.8v to 2.0v xtal1 l13 reset_ xtal2 optional 36.864-55.296mhz oscillator tb1 xtal2 x2 10-20mhz
timing diagrams 28 ns7520 datasheet 03/2006 timing diagrams timing_specifications all timing specifications consist of the relationship between a reference clock and a signal: there are bussed and non?bussed signals. non?bu ssed signals separately illustrate 0?to?1 and 1?to?0 transitions. inputs have setup/hold times versus clock rising. outputs have switching time relative to either clock rising or clock falling. note: timing relationships in this diagram are drawn without proportion to actual delay. hold setup time valid from rising edge valid from falling edge hold time setup time 1-to-0 from falling edge 0-to-1 from falling edge 1-to-0 from rising edge 0-to-1 from rising edge clock signal bus
reset_timing www.digi.com 29 reset_timing from a cold start, reset_ must be asserted until all power supplies are above their specified thresholds. an additional 8 microseconds is requ ired for oscillator settling time (allow 40ms for crystal startup). due to an internal three flip-flop delay on the external reset_ signal, after the oscillator is settled, reset_ must be asserted for three pe riods of the xtala1 clock in these situations: before release of reset af ter application of power while valid power is maintained to initiate hot reset (reset while power is at or above specified thresholds) before loss of valid power during power outage/power down the portc4 output indicates the reset state of th e chip. portc4 persists beyond the negation of reset_ for approximately 512 system clock cycles if the pll is disabled. wh en the pll is enabled, portc4 persists beyond the negation of reset_ to allow for pll lock for 100 microseconds times the ratio of the vco to xtala. reset timing parameters num description min typ max units 1 power valid before reset negated 40 ms note: reset_ should remain low for at least 40ms after power reaches 3.0v. 2 reset asserted after power valid 3 t xtala1 3 reset asserted while power valid 3 t xtala1 4 reset asserted before power invalid 3 t xtala1 4 3 3 2 1 vdd, vcc xtala1 reset_
sram timing 30 ns7520 datasheet 03/2006 sram timing bclk max frequency: 55.296 mhz operating conditions: sram timing parameters temperature: -15.00 (min) 110.00 (max) voltage: 1.60 (min) 1.40 (max) output load: 25.0pf input drive: cmos buffer num description min max unit 36 bclk high to be* valid 15.5 ns 6 bclk high to address valid 5 13.5 ns 9 bclk high to data out valid 14 ns 13 bclk high to data out high impedance 13 ns 10 data in valid to bclk high (setup) 5 ns 11 bclk high to data in invalid (hold) 3 ns 14 ta* valid to bclk high (setup) 5 ns 15 bclk high to ta* invalid (hold) 3 ns 27 bclk high to cs* valid 12.5 ns 28 bclk low to oe* valid 12.5 ns 29 bclk low to we* valid 13 ns 30 bclk high to ta* valid 13.5 ns 31 bclk high to tea* valid 16 ns 18 bclk low to a27 (cs0oe*) valid 13.5 ns 19 bclk low a26 (cs0we*) valid 13.5 ns 12 bclk high to rw* valid 13.5 ns
sram timing www.digi.com 31 sram read cs* controlled read (wait = 2) notes: 1 if the next transfer is dma, null periods betw een memory transfers can occur. thirteen clock pulses are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:0] ? 32-bit port = be[3:0] 3 the tw cycles are present when the wait field is set to 2 or more. 4 the ta* and tea*/last signal s are for reference only. t1 tw tw t2 note-1 t1 12 18 18 28 28 27 27 36 36 6 31 31 30 30 11 10 15 14 note-2 bclk ta* (note-4) tea* (note-4) ta* (input) a[27:0] be[3:0]* cs[4:0]* read d[31:0] sync oe* cs0oe* rw*
sram timing 32 ns7520 datasheet 03/2006 sram burst read cs* controlled, four word (4-2-2-2 ), burst read (wait = 2, bcyc = 01) notes: 1 if the next transfer is dma, null periods betw een memory transfers can occur. thirteen clock pulses are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:0] ? 32-bit port = be[3:0] 3 the tw cycles are present when the wait field is set to 2 or more. 4 the ta* and tea*/last signal s are for reference only. t1 tw tw t2 tw t2 tw t2 tw t2 note-1 t1 12 18 18 28 28 27 27 36 36 6 31 31 30 30 11 10 bclk ta* (note-4) tea*/last (note-4) a[27:0] be[3:0]* (note-2) cs[4:0]* read d[31:0]s sync oe* cs0oe* rw*
sram timing www.digi.com 33 sram burst read (2111) cs* controlled read (wait = 0, bcyc = 00) notes: 1 if the next transfer is dma, null periods betw een memory transfers can occur. thirteen clock pulses are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:0] ? 32-bit port = be[3:0] 3 the ta* and tea*/last signal s are for reference only. t1 t2 t2 t2 t2 note-1 t1 12 18 18 28 28 27 27 36 36 6 31 31 30 30 11 10 note-2 bclk ta* (note-3) tea* (note-3) a[27:0] be[3:0]* cs[4:0]* read d[31:0] sync oe* cs0oe* rw*
sram timing 34 ns7520 datasheet 03/2006 sram write cs controlled write (internal and external), (wait = 2) notes: 1 if the next transfer is dma, null periods betw een memory transfers can occur. thirteen clock pulses are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:0] ? 32-bit port = be[3:0] 3 the tw cycles are present when the wait field is set to 2 or more. 4 the ta* and tea*/last signal s are for reference only. t1 tw tw t2 note-1 t1 12 19 19 29 29 13 9 27 27 36 36 6 31 31 30 30 15 14 note-2 bclk ta* (note-4) tea* (note-4) ta* (input) a[27:0] be[3:0]* cs[4:0]* write d[31:0] sync we* cs0we* rw*
sram timing www.digi.com 35 sram burst write cs controlled, four word (4-2-2-2 ), burst write (wait = 2, bcyc = 01) notes: 1 if the next transfer is dma, null periods betw een memory transfers can occur. thirteen clock pulses are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:0] ? 32-bit port = be[3:0] 3 the tw cycles are present when the wait field is set to 2 or more. 4 the ta* and tea*/last signal s are for reference only. t1 tw tw t2 tw t2 tw t2 tw t2 note-1 t1 12 19 19 29 29 13 9 27 27 36 36 6 31 31 30 30 bclk ta* (note-4) tea*/last (note-4) a[27:0] be[3:0]* (note-2) cs[4:0]* write d[31:0] sync we* cs0we* rw*
sram timing 36 ns7520 datasheet 03/2006 sram oe read oe* controlled read (wait = 2) notes: 1 at least one null period occurs between memory transfers. more null pe riods can occur if the next transfer is dma. thirteen clock puls es are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:0] ? 32-bit port = be[3:0] 3 the tw cycles are present when the wait field is set to 2 or more. 4 the ta* and tea*/last signal s are for reference only. t1 tw t2 note-1 t1 12 18 18 28 28 27 27 36 36 6 31 31 30 30 11 10 15 14 note-2 bclk ta* (note-4) tea*/last (note-4) ta* (input) a[27:0] be[3:0]* cs[4:0]* read d[31:0] async oe* cs0oe* rw*
sram timing www.digi.com 37 sram oe burst read oe* controlled, four word (3-2-2-2), burst read (wait = 2, bcyc = 01) notes: 1 at least one null period occurs between memory transfers. more null pe riods can occur if the next transfer is dma. thirteen clock puls es are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:0] ? 32-bit port = be[3:0] 3 the tw cycles are present when the wait field is set to 2 or more. 4 the ta* and tea*/last signal s are for reference only. t1 tw t2 tw t2 tw t2 tw t2 note-1 t1 12 18 18 28 28 27 27 36 36 6 31 31 30 30 11 10 bclk ta* (note-4) tea*/last (note-4) a[27:0] be[3:0]* (note-2) cs[4:0]* read d[31:0] async oe* cs0oe* rw*
sram timing 38 ns7520 datasheet 03/2006 sram we write we* controlled write (wait = 2) notes: 1 at least one null period occurs between memory transfers. more null pe riods can occur if the next transfer is dma. thirteen clock puls es are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:0] ? 32-bit port = be[3:0] 3 the tw cycles are present when the wait field is set to 2 or more. 4 the ta* and tea*/last signal s are for reference only. t1 tw t2 note-1 t1 12 19 19 29 29 13 9 27 27 36 36 6 31 31 30 30 15 14 note-2 bclk ta* (note-4) tea*/last (note-4) ta* (input) a[27:0] be[3:0]* cs[4:0]* write d[31:0] async we* cs0we* rw*
sram timing www.digi.com 39 sram we burst write we* controlled, four word (3-2-2-2), burst write (wait = 2, bcyc = 01) notes: 1 at least one null period occurs between memory transfers. more null pe riods can occur if the next transfer is dma. thirteen clock puls es are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:0] ? 32-bit port = be[3:0] 3 the tw cycles are present when the wait field is set to 2 or more. 4 the ta* and tea*/last signal s are for reference only. t1 tw t2 tw t2 tw t2 tw t2 note-1 t1 12 19 19 29 29 13 9 27 27 36 36 6 31 31 30 30 note-2 bclk ta* (note-4) tea*/last (note-4) a[27:0] be[3:0]* cs[4:0]* write d[31:0] async we* cs0we* rw*
sdram timing 40 ns7520 datasheet 03/2006 sdram timing bclk max frequency: 55.296 mhz operating conditions: sdram timing parameters temperature: -15.00 (min) 110.00 (max) voltage: 1.60 (min) 1.40 (max) output load: 25.0pf input drive: cmos buffer num description min max unit 36 bclk high to be*/dqm* valid 15.5 ns 6 bclk high to non-muxed address valid 5 13.5 ns 9 bclk high to data out valid 14 ns 13 bclk high to data out high impedance 13 ns 10 data in valid to bclk high (setup) 5 ns 11 bclk high to data in invalid (hold) 3 ns 27 bclk high to cs* valid 15.5 ns 30 bclk high to ta* valid 13.5 ns 31 bclk high to tea* valid 16 ns 37 bclk high to porta2/amux valid 14 ns 35 bclk high to muxed address valid 6 14.5 ns 34 bclk high to cas* valid 12 ns 12 bclk high to rw* valid 13.5 ns
sdram timing www.digi.com 41 sdram read sdram read, cas latency = 2 notes: 1 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:2] ? 32-bit port = be[3:0] 2 the precharge and/or active co mmands are not always present. these commands depend on the address of the previous sdram access. 3 if cas latency = 3, 2 nops occur between the read and burst terminate commands. 4 if cas latency = 3, 3 inhibits occur after burst terminate. 5 the ta* and tea*/last signal s are for reference only. t1 t2 t1 prechg active read nop bterm inhibit inhibit 12 34 34 34 34 34 34 34 34 34 34 34 27 27 36 36 35 35 6 37 37 31 31 30 30 11 10 a10 bclk ta* (note-5) tea*/last* (note-5) porta2/amux non-muxed address muxed address be[3:0]* (dqm) read d[31:0] cs[4:0]* cas3* (ras) cas2* (cas) cas1* (we) cas0* (a10/ap) rw*
sdram timing 42 ns9360 datasheet 03/2006 sdram read sdram read, cas latency = 1 notes: 1 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:2] ? 32-bit port = be[3:0] 2 the precharge and/or active co mmands are not always present. these commands depend on the address of the previous sdram access. 3 the ta* and tea*/last signal s are for reference only. t1 t2 t1 prechg active read bterm inhibit 12 34 34 34 34 34 34 34 34 34 34 34 27 27 36 36 35 35 6 37 37 31 31 30 30 11 10 a10 bclk ta* (note-3) tea*/last* (note-3) porta2/amux non-muxed address muxed address be[3:0]* (dqm) read d[31:0] cs[4:0]* cas3* (ras#) cas2* (cas#) cas1* (we#) cas0* (a10/ap) rw*
sdram timing www.digi.com 43 sdram burst read sdram read, cas latency = 2 notes: 1 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:2] ? 32-bit port = be[3:0] 2 the precharge and/or active co mmands are not always present. these commands depend on the address of the previous sdram access. 3 if cas latency = 3, 5 nops occur between the read and burst terminate commands. 4 if cas latency = 3, 3 inhibits occur after burst terminate. 5 the ta* and tea*/last signal s are for reference only. t1 t2 t2 t2 t2 t1 prechg active read nop nop nop nop bterm inhibit inhibit 12 34 34 34 34 34 34 34 34 34 34 34 27 27 36 36 35 35 6 37 37 31 31 30 30 11 10 a10 bclk ta* (note-5) tea*/last* (note-5) porta2/amux non-muxed address muxed address be*[3:0]* (dqm) read d[31:0] cs[4:0]* cas3* (ras) cas2* (cas) cas1* (we) cas0* (a10/ap) rw*
sdram timing 44 ns9360 datasheet 03/2006 sdram burst read sdram read, cas latency = 1 notes: 1 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:2] ? 32-bit port = be[3:0] 2 the precharge and/or active co mmands are not always present. these commands depend on the address of the previous sdram access. 3 if cas latency = 3, 5 nops occur between the read and burst terminate commands. 4 if cas latency = 3, 3 inhibits occur after burst terminate. 5 the ta* and tea*/last signal s are for reference only. t1 t2 t2 t2 t2 t1 prechg active read nop nop nop bterm inhibit 12 34 34 34 34 34 34 34 34 34 34 34 27 27 36 36 35 35 6 37 37 31 31 30 30 11 10 a10 bclk ta* (note-5) tea*/last* (note-5) porta2/amux non-muxed address muxed address be[3:0]* (dqm) read d[31:0] cs[4:0]* cas3* (ras) cas2* (cas) cas1* (we) cas0* (a10/ap) rw*
sdram timing www.digi.com 45 sdram write sdram write notes: 1 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:2] ? 32-bit port = be[3:0] 2 the precharge and/or active co mmands are not always present. these commands depend on the address of the previous sdram access. 3 the ta* and tea*/last signal s are for reference only. t1 t2 t1 prechg active write inhibit 12 34 34 34 34 34 34 34 34 34 34 34 27 27 13 9 36 36 35 35 6 37 37 31 31 30 30 a10 note-1 bclk ta* (note-3) tea*/last* (note-3) porta2/amux non-muxed address muxed address be[3:0]* (dqm) write d[31:0] cs[4:0]* cas3* (ras) cas2* (cas) cas1* (we) cas0* (a10/ap) rw*
sdram timing 46 ns9360 datasheet 03/2006 sdram burst write sdram burst write notes: 1 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:2] ? 32-bit port = be[3:0] 2 the precharge and/or active co mmands are not always present. these commands depend on the address of the previous sdram access. when the active command is not present, parameter #35 is valid duri ng the write (t2) cycle. 3 the ta* and tea*/last signal s are for reference only. t1 t2 t2 t2 t2 t1 prechg active write write write write inhibit 12 34 34 34 34 34 34 34 34 34 34 34 27 27 36 36 13 9 35 35 6 37 37 31 31 30 30 a10 bclk ta* (note-3) tea*/last* (note-3) porta2/amux non-muxed address muxed address write d[31:0]1 be[3:0]* (dqm) cs[4:0]* cas3* (ras) cas2* (cas) cas1* (we) cas0* (a10/ap) rw*
sdram timing www.digi.com 47 sdram load mode sdram refresh prechg nop load 35 35 34 34 34 34 34 34 34 34 34 34 27 27 op code bclk cs[4:0]* cas3* (ras) cas2* (cas) cas1* (we) cas0* (a10/ap) a[13:0] prechg inhibit refresh 34 34 34 34 34 34 34 34 27 27 27 27 bclk cs[4:0]* cas3* (ras) cas2* (cas) cas1* (we) cas0* (a10/ap)
fp dram timing 48 ns9360 datasheet 03/2006 fp dram timing bclk max frequency: 55.296 mhz operating conditions: fp dram timing parameters temperature: -15.00 (min) 110.00 (max) voltage: 1.60 (min) 1.40 (max) output load: 25.0pf input drive: cmos buffer num description min max unit 36 bclk high to be* valid 15.5 ns 6 bclk high to address valid 5 13.5 ns 9 bclk high to data out valid 14 ns 13 bclk high to data out high impedance 13 ns 10 data in valid to bclk high (setup) 5 ns 11 bclk high to data in invalid (hold) 3 ns 14 ta* valid to bclk high (setup) 5 ns 15 bclk high to ta* invalid (hold) 3 ns 28 bclk low to oe* valid 12.5 ns 29 bclk low to we* valid 13 ns 30 bclk high to ta* valid 13.5 ns 31 bclk high to tea* valid 16 ns 37 bclk high to porta2/amux valid 14 ns 35 bclk high to muxed address valid 6 14.5 ns 43 bclk low to cas* valid 13 ns 27 bclk low to ras* valid 12 ns 12 bclk high to rw* valid 13.5 ns
fp dram timing www.digi.com 49 fp dram read fast page read notes: 1 if the next transfer is dma, null periods betw een memory transfers can occur. thirteen clock pulses are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:2] ? 32-bit port = be[3:0] 3 port size determines whic h cas signals are active: ? 8-bit port = cas3* ? 16-bit port = cas[3:2] ? 32-bit port = cas[3:0] 4 the ta* and tea*/last signal s are for reference only. t1 tw t2 note-1 t1 12 37 37 43 43 27 27 28 28 35 35 6 36 36 31 31 30 30 11 10 15 14 note-2 note-3 bclk ta* (note-4) tea*/last (note-4) ta* (input) be[3:0]* non-muxed address muxed address read d[31:0]1 oe* ras[4:0]*1 cas[3:0]*1 porta2/amux rw*
fp dram timing 50 ns9360 datasheet 03/2006 fp dram burst read fast page burst read notes: 1 if the next transfer is dma, null periods betw een memory transfers can occur. thirteen clock pulses are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:2] ? 32-bit port = be[3:0] 3 port size determines whic h cas signals are active: ? 8-bit port = cas3* ? 16-bit port = cas[3:2] ? 32-bit port = cas[3:0] 4 the ta* and tea*/last signal s are for reference only. t1 tw t2 tw t2 tw t2 tw t2 note-1 t1 12 37 37 43 43 27 27 28 28 35 6 36 36 31 31 30 30 11 10 note-2 note-3 bclk ta* (note-4) tea*/last (note-4) be[3:0]* non-muxed address muxed address read d[31:0] oe* ras[4:0]* cas[3:0]* porta2/amux rw*
fp dram timing www.digi.com 51 fp dram write fast page write notes: 1 if the next transfer is dma, null periods betw een memory transfers can occur. thirteen clock pulses are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:2] ? 32-bit port = be[3:0] 3 port size determines whic h cas signals are active: ? 8-bit port = cas3* ? 16-bit port = cas[3:2] ? 32-bit port = cas[3:0] 4 the ta* and tea*/last signal s are for reference only. t1 tw t2 note-1 t1 12 37 37 43 43 27 27 29 29 13 9 35 6 36 36 31 31 30 30 15 14 note-2 note-3 bclk ta* (note-4) tea*/last (note-4) ta* (input) be[3:0]* non-muxed address muxed address write d[31:0] we* (fp)ras[4:0]* (fp)cas[3:0]* porta2/amux rw*
fp dram timing 52 ns9360 datasheet 03/2006 fp dram burst write fast page burst write notes: 1 if the next transfer is dma, null periods betw een memory transfers can occur. thirteen clock pulses are required for dma context switching. 2 port size determines which by te enable signals are active: ? 8-bit port = be3* ? 16-bit port = be[3:2] ? 32-bit port = be[3:0] 3 port size determines whic h cas signals are active: ? 8-bit port = cas3* ? 16-bit port = cas[3:2] ? 32-bit port = cas[3:0] 4 the ta* and tea*/last signal s are for reference only. 5 the bcyc field should never be set to 00. t1 tw t2 tw t2 tw t2 tw t2 note-1 t1 12 37 37 43 43 43 27 27 29 29 13 9 35 6 36 36 31 31 30 30 note-2 note-3 bclk ta* (note-4) tea*/last (note-4) be[3:0]* non-muxed address muxed address writed[31:0] we* ras[4:0]* cas[3:0]* portc3/amux rw*
fp dram timing www.digi.com 53 fp_refresh_cycles fast page refresh (rcyc = 00) fast page refresh (rcyc = 01) rf1 rf2 rf3 rf4 rf5 rf6 rf7 rf8 t1 12 12 43 43 43 43 43 43 43 43 27 27 bclk ras[4:0]* cas3* cas2* cas1* cas0* we* rf1 rf2 rf3 rf4 rf5 rf6 rf8 t1 12 12 43 43 43 43 43 43 43 43 27 27 ftp rf h(rcyc01) bclk ras[4:0]* cas3* cas2* cas1* cas0* we*
fp dram timing 54 ns9360 datasheet 03/2006 fast page refresh (rcyc = 10) fast page refresh (rcyc = 11) rf1 rf2 rf3 rf4 rf5 rf8 t1 12 12 43 43 43 43 43 43 43 43 27 27 bclk ras[4:0]* cas3* cas2* cas1* cas0* we* rf1 rf2 rf3 rf4 rf8 t1 12 12 43 43 43 43 43 43 43 43 27 27 bclk ras[4:0]* cas3* cas2* cas1* cas0* we*
ethernet timing www.digi.com 55 ethernet timing operating conditions: ethernet timing parameters ethernet phy timing temperature: -15.00 (min) 110.00 (max) voltage: 1.60 (min) 1.40 (max) output load: 25.0pf input drive: cmos buffer num description min max unit 44 txclk high to txd*, txen, txer valid 11.5 ns 45 rxd*, rxer, rxdv, txcol, rxcrs valid to rxclk high (setup) 3 ns 46 rxclk high to rxd*, rxer, rxdv, txcol, rxcrs hold time 2 ns 49 mdc high to mdio valid 50 ns 47 mdio valid to mdc high (setup) 3 ns 48 mdc high to mdio hold time 3 ns 50 rxclk high to rspf* valid 15.5 ns 52 reject* valid to rxclk high (setup) 3 ns 53 reject* valid from rxclk high (hold) 1.5 ns 49 48 47 46 45 44 txclk txd[3:0],txen,txer rxclk rxd[3:0],rxer,rxdv,crs,col mdio (input) mdc mdio (output)
ethernet timing 56 ns9360 datasheet 03/2006 ethernet cam timing 53 51 52 50 50 rxclk rpsf_ reject_
jtag timing www.digi.com 57 jtag timing operating conditions: jtag arm ice timing parameters jtag arm ice timing diagram temperature: -15.00 (min) 110.00 (max) voltage: 1.60 (min) 1.40 (max) output load: 25.0pf input drive: cmos buffer num description min max units 54 tck to tdo valid 21 ns 55 tck to tdo highz 21 ns 56 tdi setup to tck rising 1 ns 57 tdi hold from tck rising 3 ns 58 trst* width 1 t tck 60 tms setup to tck rising 1 ns 61 tms hold from tck rising 3 ns 61 60 57 56 55 54 58 58 tck tdo tdi trst_ tms
jtag timing 58 ns9360 datasheet 03/2006 jtag bscan timing parameters jtag bscan timing diagram num description min max units 62 tck to tdo valid 21 ns 63 tck to tdo highz 21 ns 64 tdi setup to tck rising 1 ns 65 tdi hold from tck rising 3 ns 66 trst* width 1 t tck 68 tms setup to tck rising 1 ns 69 tms hold to tck rising 3 ns 69 68 65 64 63 62 66 66 tck tdo tdi trst_ tms
external dma timing www.digi.com 59 external dma timing bclk max frequency: 55.296 mhz operating conditions: external dma timing parameters fly-by external dma notes: 1 the memory signals are data[31: 0], addr[27:0], be[3:0], cs/r as[4:0], cas[3:0], rw, oe*. we*, and portc3/amux. the timing of these signal s depends on how the memory is configured (sync sram, async sram, fp dram, or sdram). 2 the done* signal works as an input only when the dma channel is configured as fly-by write. temperature: -15.00 (min) 110.00 (max) voltage: 1.60 (min) 1.40 (max) output load: 25.0pf input drive: cmos buffer num description min max unit 72 bclk high to dack* valid 14 ns 75 bclk high to done* (output) valid 15 ns 70 dreq* low to bclk high (setup) 5 ns 71 bclk high to dreq* valid (hold) 0 ns 73 done* (input) valid bclk high (setup) 5 ns 74 blck high to done* (input) valid (hold) 0 ns t1 tw t2 75 75 72 72 74 73 71 70 note2 bclk mem signals (note-1) dreq* dack* done* (output) done* (input)
external dma timing 60 ns9360 datasheet 03/2006 memory-to-memory external dma notes: 1 a null period sometimes occurs between memory cycles. 2 the memory signals are data[31: 0], addr[27:0], be[3:0], cs/r as[4:0], cas[3:0], rw, oe*. we*, and porta2/amux. the timing of these signal s depends on how the memory is configured (sync sram, async sram, fp dram, or sdram). t1 tw t2 note-1 t1 tw t2 75 75 75 75 72 72 72 72 71 70 71 70 bclk mem signals (note-2) r/w dreq* dack* done* (output)
serial internal/external timing www.digi.com 61 serial internal/external timing operating conditions: note: spi timing diagrams are in chapter 10, "seria l controller module." see figure 25, "spi master mode 0 and 1 two-byte transfer," on page 219 and figure 26, "spi slave mode 0 and 1 two-byte transfer," on page 222. only spi modes 0 and 1 are supported. serial internal ti ming characteristics serial external timing characteristics temperature: -15.00 (min) 110.00 (max) voltage: 1.60 (min) 1.40 (max) output load: 25.0pf input drive: cmos buffer num description min max unit 76 sclk to enable high 1 t sclk 77 sclk to txd (porta7/c7) 1 t sys *ns 78 rxd (porta3/c3) setup to sclk 1 ns 79 rxd hold to sclk 1 ns * the t sys parameter represents one period of the internal system clock. num description min max unit 80 sclk frequency 10 mhz sclk duty cycle 45 55 % 81 sclk to enable 1 t sclk 82 sclk to txd (porta7/c7) 2t sys *ns 83 rxd (porta3/c3) setup to sclk 2 ns 84 rxd hold to sclk 1.5 ns * the t sys parameter represents one period of the internal system clock.
serial internal/external timing 62 ns9360 datasheet 03/2006 synchronous serial internal clock synchronous serial external clock 79 78 77 77 76 76 sclk enable txd rxd 84 83 82 82 81 81 80 80 sclk enable txd rxd
gpio timing www.digi.com 63 gpio timing operating conditions: gpio timing parameters gpio timing diagram temperature: -15.00 (min) 110.00 (max) voltage: 1.60 (min) 1.40 (max) output load: 25.0pf input drive: cmos buffer num description min max unit 85 gpio (setup) to bclk rising 3 ns 86 gpio (hold) from bclk rising 0 ns 87 bclk to gpio (output) 17 ns 87 86 85 bclk gpio (input) gpio (output)
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